12: Shift Registers
- Page ID
- 986
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\(\newcommand{\avec}{\mathbf a}\) \(\newcommand{\bvec}{\mathbf b}\) \(\newcommand{\cvec}{\mathbf c}\) \(\newcommand{\dvec}{\mathbf d}\) \(\newcommand{\dtil}{\widetilde{\mathbf d}}\) \(\newcommand{\evec}{\mathbf e}\) \(\newcommand{\fvec}{\mathbf f}\) \(\newcommand{\nvec}{\mathbf n}\) \(\newcommand{\pvec}{\mathbf p}\) \(\newcommand{\qvec}{\mathbf q}\) \(\newcommand{\svec}{\mathbf s}\) \(\newcommand{\tvec}{\mathbf t}\) \(\newcommand{\uvec}{\mathbf u}\) \(\newcommand{\vvec}{\mathbf v}\) \(\newcommand{\wvec}{\mathbf w}\) \(\newcommand{\xvec}{\mathbf x}\) \(\newcommand{\yvec}{\mathbf y}\) \(\newcommand{\zvec}{\mathbf z}\) \(\newcommand{\rvec}{\mathbf r}\) \(\newcommand{\mvec}{\mathbf m}\) \(\newcommand{\zerovec}{\mathbf 0}\) \(\newcommand{\onevec}{\mathbf 1}\) \(\newcommand{\real}{\mathbb R}\) \(\newcommand{\twovec}[2]{\left[\begin{array}{r}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\ctwovec}[2]{\left[\begin{array}{c}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\threevec}[3]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\cthreevec}[3]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\fourvec}[4]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\cfourvec}[4]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\fivevec}[5]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\cfivevec}[5]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\mattwo}[4]{\left[\begin{array}{rr}#1 \amp #2 \\ #3 \amp #4 \\ \end{array}\right]}\) \(\newcommand{\laspan}[1]{\text{Span}\{#1\}}\) \(\newcommand{\bcal}{\cal B}\) \(\newcommand{\ccal}{\cal C}\) \(\newcommand{\scal}{\cal S}\) \(\newcommand{\wcal}{\cal W}\) \(\newcommand{\ecal}{\cal E}\) \(\newcommand{\coords}[2]{\left\{#1\right\}_{#2}}\) \(\newcommand{\gray}[1]{\color{gray}{#1}}\) \(\newcommand{\lgray}[1]{\color{lightgray}{#1}}\) \(\newcommand{\rank}{\operatorname{rank}}\) \(\newcommand{\row}{\text{Row}}\) \(\newcommand{\col}{\text{Col}}\) \(\renewcommand{\row}{\text{Row}}\) \(\newcommand{\nul}{\text{Nul}}\) \(\newcommand{\var}{\text{Var}}\) \(\newcommand{\corr}{\text{corr}}\) \(\newcommand{\len}[1]{\left|#1\right|}\) \(\newcommand{\bbar}{\overline{\bvec}}\) \(\newcommand{\bhat}{\widehat{\bvec}}\) \(\newcommand{\bperp}{\bvec^\perp}\) \(\newcommand{\xhat}{\widehat{\xvec}}\) \(\newcommand{\vhat}{\widehat{\vvec}}\) \(\newcommand{\uhat}{\widehat{\uvec}}\) \(\newcommand{\what}{\widehat{\wvec}}\) \(\newcommand{\Sighat}{\widehat{\Sigma}}\) \(\newcommand{\lt}{<}\) \(\newcommand{\gt}{>}\) \(\newcommand{\amp}{&}\) \(\definecolor{fillinmathshade}{gray}{0.9}\)- 12.1: Introduction to Shift Registers
- This page discusses shift registers as sequential logic components that store data based on past inputs, thereby delaying signals by "n" clock cycles. They convert parallel data to serial format for efficient transmission in microprocessors and peripherals. Various types include serial-in/serial-out and parallel-in/serial-out configurations. Additionally, specialized counter circuits utilizing shift registers can generate complex waveforms and simplify wiring on circuit boards.
- 12.2: Shift Registers- Serial-in, Serial-out
- This page covers SISO shift registers that delay data by one clock period per stage, emphasizing clock synchronization for output reliability. It discusses the critical setup and hold times for cascading flip-flops in multi-stage configurations and provides examples from the CD4000 series.
- 12.3: Shift Registers- Parallel-in, Serial-out (PISO) Conversion
- This page covers PISO shift registers, detailing their functionality for simultaneous data input and serial output using D Flip-Flops. It explains both synchronous and asynchronous loading processes, particularly with models SN74ALS166 and CD4014B, which allow output setting/resetting without a clock signal.
- 12.4: Shift Registers- Serial-in, Parallel-out (SIPO) Conversion
- This page covers details about serial-in, parallel-out shift registers, which convert serial data to parallel form for applications like LED control. It notes the typical 8-bit size limitations and contrasts with serial-in, serial-out registers. Specific models from Texas Instruments, like the CD4094B, are discussed for their operational features, including latching, clock input, and strobe output.
- 12.5: Universal Shift Registers- Parallel-in, Parallel-out
- This page covers the functionality and operation of shift registers, specifically the 74LS395 and SN74ALS299 models. It explains how these devices manage parallel data inputs, data shifting in both directions, and control signals. The 74LS395 is discussed for its configurations enabling parallel loading and shifting, while the SN74ALS299 details operations including modes for shifting left/right and parallel load, tri-state buffer functions, and practical applications like keypad integration.
- 12.6: Ring Counters
- This page covers the operation and applications of shift registers, specifically ring and Johnson counters. It highlights the design aspects of ring counters, emphasizing proper initialization, while explaining how Johnson counters improve functionality by utilizing feedback and requiring fewer stages.