9: Combinational Logic Functions
- Page ID
- 951
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\(\newcommand{\avec}{\mathbf a}\) \(\newcommand{\bvec}{\mathbf b}\) \(\newcommand{\cvec}{\mathbf c}\) \(\newcommand{\dvec}{\mathbf d}\) \(\newcommand{\dtil}{\widetilde{\mathbf d}}\) \(\newcommand{\evec}{\mathbf e}\) \(\newcommand{\fvec}{\mathbf f}\) \(\newcommand{\nvec}{\mathbf n}\) \(\newcommand{\pvec}{\mathbf p}\) \(\newcommand{\qvec}{\mathbf q}\) \(\newcommand{\svec}{\mathbf s}\) \(\newcommand{\tvec}{\mathbf t}\) \(\newcommand{\uvec}{\mathbf u}\) \(\newcommand{\vvec}{\mathbf v}\) \(\newcommand{\wvec}{\mathbf w}\) \(\newcommand{\xvec}{\mathbf x}\) \(\newcommand{\yvec}{\mathbf y}\) \(\newcommand{\zvec}{\mathbf z}\) \(\newcommand{\rvec}{\mathbf r}\) \(\newcommand{\mvec}{\mathbf m}\) \(\newcommand{\zerovec}{\mathbf 0}\) \(\newcommand{\onevec}{\mathbf 1}\) \(\newcommand{\real}{\mathbb R}\) \(\newcommand{\twovec}[2]{\left[\begin{array}{r}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\ctwovec}[2]{\left[\begin{array}{c}#1 \\ #2 \end{array}\right]}\) \(\newcommand{\threevec}[3]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\cthreevec}[3]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \end{array}\right]}\) \(\newcommand{\fourvec}[4]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\cfourvec}[4]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \end{array}\right]}\) \(\newcommand{\fivevec}[5]{\left[\begin{array}{r}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\cfivevec}[5]{\left[\begin{array}{c}#1 \\ #2 \\ #3 \\ #4 \\ #5 \\ \end{array}\right]}\) \(\newcommand{\mattwo}[4]{\left[\begin{array}{rr}#1 \amp #2 \\ #3 \amp #4 \\ \end{array}\right]}\) \(\newcommand{\laspan}[1]{\text{Span}\{#1\}}\) \(\newcommand{\bcal}{\cal B}\) \(\newcommand{\ccal}{\cal C}\) \(\newcommand{\scal}{\cal S}\) \(\newcommand{\wcal}{\cal W}\) \(\newcommand{\ecal}{\cal E}\) \(\newcommand{\coords}[2]{\left\{#1\right\}_{#2}}\) \(\newcommand{\gray}[1]{\color{gray}{#1}}\) \(\newcommand{\lgray}[1]{\color{lightgray}{#1}}\) \(\newcommand{\rank}{\operatorname{rank}}\) \(\newcommand{\row}{\text{Row}}\) \(\newcommand{\col}{\text{Col}}\) \(\renewcommand{\row}{\text{Row}}\) \(\newcommand{\nul}{\text{Nul}}\) \(\newcommand{\var}{\text{Var}}\) \(\newcommand{\corr}{\text{corr}}\) \(\newcommand{\len}[1]{\left|#1\right|}\) \(\newcommand{\bbar}{\overline{\bvec}}\) \(\newcommand{\bhat}{\widehat{\bvec}}\) \(\newcommand{\bperp}{\bvec^\perp}\) \(\newcommand{\xhat}{\widehat{\xvec}}\) \(\newcommand{\vhat}{\widehat{\vvec}}\) \(\newcommand{\uhat}{\widehat{\uvec}}\) \(\newcommand{\what}{\widehat{\wvec}}\) \(\newcommand{\Sighat}{\widehat{\Sigma}}\) \(\newcommand{\lt}{<}\) \(\newcommand{\gt}{>}\) \(\newcommand{\amp}{&}\) \(\definecolor{fillinmathshade}{gray}{0.9}\)- 9.1: Introduction to Combinational Logic Functions
- This page discusses combinational logic, which yields consistent outputs irrespective of input order, contrasting with sequential logic that relies on timing. It explains that combinational circuits handle tasks such as arithmetic and logic operations, while sequential circuits focus on the correct sequence of events.
- 9.2: Half-Adder
- This page introduces the half-adder, a combinational logic device that adds two binary digits, with inputs 'a' and 'b', and outputs the sum (Σ) and carry out (Cout). It explains how to derive its truth table, identifying Σ as an XOR gate and Cout as an AND gate, while indicating that related concepts will be explored in the next section.
- 9.3: Full-Adder
- This page covers the construction and optimization of binary adders, detailing the limitations of half-adders and the role of full adders in adding multiple binary digits. It explains the design of three-input adders and the chaining of adders for varying bit lengths.
- 9.4: Decoder
- This page covers decoders, circuits converting encoded signals to outputs, focusing on line decoders like 1-to-2 and 2-to-4 types. It describes how larger decoders can be built from simpler ones, akin to binary adders, and highlights their practical use in efficient device selection with fewer control lines. The page advocates for logical design as a superior approach compared to basic gate translations in circuit design.
- 9.5: Encoder
- This page explains encoders, circuits that convert multiple signals into coded outputs. It covers creating a 2-to-1 line encoder truth table, managing unused inputs, and includes an example of a binary to 7-segment encoder where undefined inputs are treated as "don't care." The content details circuit equation simplification using Karnaugh maps and presents the resulting circuit and ladder diagram.
- 9.6: Demultiplexers
- This page explains demultiplexers (dmux), which route a single input signal to multiple outputs, differentiating them from decoders. It includes details on their schematic representation and truth tables, such as for a 1-to-2 dmux. It also discusses how demultiplexers can be expanded by increasing inputs or outputs, often through line decoders, exemplifying the concept with a two-bit 1-to-2 dmux and the construction of a 1-to-4 dmux using 1-to-2 demultiplexers.
- 9.7: Multiplexers
- This page explains multiplexers (mux), devices that have multiple inputs and a single output, illustrated through schematic symbols and truth tables, including for a 2-to-1 mux. It notes the use of a 1-to-2 decoder for simplification and describes how multiplexers can be expanded to forms like a 4-to-1 mux. The page also highlights the potential confusion between multiplexers and demultiplexers due to their similar names and functions.
- 9.8: Using Multiple Combinational Circuits
- This page covers the design of a circuit that displays a four-digit number on a 7-segment display using a binary-to-7-segment encoder, with 16 primary inputs and two selection inputs for digit display. It emphasizes modular design for managing circuit complexity and mentions potential enhancements through sequential circuits for future simultaneous digit display improvements.