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- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/04%3A_Strategies_and_Interface_I_O/4.02%3A_Mechanisms_of_interruption-_recognition_of_vector_and_interrupt_priorityThe following section introduces the learner to Interruptions that occur in Programmed I/O
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/04%3A_Strategies_and_Interface_I_O/4.04%3A_Unit_4_SummaryAt the end of this unit, the learners will be conversant with the strategies of I/O interfaces. This involves accessibility of devices connected to the processor and where I/O transfers must take plac...At the end of this unit, the learners will be conversant with the strategies of I/O interfaces. This involves accessibility of devices connected to the processor and where I/O transfers must take place between them and the processor. the various access methods, e.g. polling, interrupt and DMA. The interrupt process is also learned in this section.
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/01%3A_Functional_Organization/1.02%3A_Micro-architectures_-_Achievements_Connections_by_Wires_and_MicroprogrammedThis section introduces the learners to the micro-architecture of the computer. That is the resources and methods used to achieve specifications.
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/06%3A_Ancillary_Materials/6.03%3A_Mid_term_Exam_2During any given bus cycle, one of the system components connected to the system bus is given control of the bus. The CPU with its bus control logic is normally the master, but other specially designe...During any given bus cycle, one of the system components connected to the system bus is given control of the bus. The CPU with its bus control logic is normally the master, but other specially designed components can gain control of the bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master.
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/01%3A_Functional_Organization/1.03%3A_Instructions_plumbing_and_Instruction_level_parallelism_(ILP)This section introduces the learners to the Instruction plumbing and Instruction level parallelism (ILP). Basically this all about how many of the operations in a computer program can be performed sim...This section introduces the learners to the Instruction plumbing and Instruction level parallelism (ILP). Basically this all about how many of the operations in a computer program can be performed simultaneously
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/04%3A_Strategies_and_Interface_I_OThis section introduces the learners to the strategies of I/O interfaces. They include: polled, interrupt driven and DMA.
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/02%3A_Multiprocessing/2.03%3A_The_Multicore_and_Multiprocessor_SegmentsThis can mean different things depending on the exact architecture, but it basically means that a certain subset of the CPU’s components is duplicated, so that multiple “cores” can work in parallel on...This can mean different things depending on the exact architecture, but it basically means that a certain subset of the CPU’s components is duplicated, so that multiple “cores” can work in parallel on separate operations. Now, this can mean different things depending on the exact architecture, but it basically means that a certain subset of the CPU’s components is duplicated, so that multiple “cores” can work in parallel on separate operations.
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/06%3A_Ancillary_MaterialsIntroduction This assessment consists of an assignment, a sitting CAT and a final exam. The assiment has a weight of 20 while the CAt has a weight of 30. The final exam has a weighting of 50, giving a...Introduction This assessment consists of an assignment, a sitting CAT and a final exam. The assiment has a weight of 20 while the CAt has a weight of 30. The final exam has a weighting of 50, giving a total of 100 percent.
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/00%3A_Front_Matter/04%3A_About_this_BookMostafa Abd-El-Barr , Hesham El-Rewini; Fundamentals of Computer Organization and Architecture and Advanced Computer Architecture and Parallel Processing; Edition 2: ISBN-13: 978-0471703808 Representa...Mostafa Abd-El-Barr , Hesham El-Rewini; Fundamentals of Computer Organization and Architecture and Advanced Computer Architecture and Parallel Processing; Edition 2: ISBN-13: 978-0471703808 Representation of digital and analog values - sampling and quantization; Standards multimedia (audio, music, graphics, image, telephony, video, TV); Coding and decoding multimedia systems; Compression and decompression of data; Input devices: mice,
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/04%3A_Strategies_and_Interface_I_O/4.03%3A_Direct_Memory_Access_(DMA)This section introduces the learners to the DMA programmed I/O which provides access to the microprocessor between devices operating at different speeds
- https://workforce.libretexts.org/Bookshelves/Information_Technology/Information_Technology_Hardware/Advanced_Computer_Organization_Architecture_(Njoroge)/00%3A_Front_Matter/05%3A_Pre-AssessmentComputer performance: is characterized by the amount of useful work accomplished by a computer system or computer network compared to the time and resources used I/O: Accessories that allow computer t...Computer performance: is characterized by the amount of useful work accomplished by a computer system or computer network compared to the time and resources used I/O: Accessories that allow computer to perform specific tasks; Receive information for processing, Return the results of processing, Store information The various components are assumed to be in place and the task is to investigate the organizational structure to verify that the computer parts operate.