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6.3: Mid term Exam 2

  • Page ID
    14859
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    Mid term Exam 2 (30 %)

    Instructions

    Answer all the questions in this paper

    1. (a). Draw the block diagram of a DMA controller (10 marks)

    (b). explain its functioning (5 marks)

    2.Describe the architecture of a shared memory multiprocessor (5 marks)

    Grading Scheme

    1.(a). Correct diagram 10 marks

    (b). Correct function 2 marks each (max 10)

    2. Any correct answer 2 marks each (max 10)

    Feedback

    1. (a). Draw the block diagram of a DMA controller

    (b). Explain its functioning

    During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. The CPU with its bus control logic is normally the master, but other specially designed components can gain control of the bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master.

    2. Describe the architecture of a shared memory multiprocessor

    • Processors have their own connection to memory
    • Processors are capable of independent execution and control
    • Have a single OS for the whole system, support both processes and threads, and appear as a common multiprogrammed system
    • Can be used to run multiple sequential programs concurrently or parallel programs
    • Suitable for parallel programs where threads can follow different code (task-level-parallelism)

    6.3: Mid term Exam 2 is shared under a CC BY-SA license and was authored, remixed, and/or curated by Harrison Njoroge.

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