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6.1: Final Exam

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    Final Exam (50 %)


    1. Answer question one and any other two

    2. Question one carries 30 marks

    3. Other questions carry 20 marks each


    1. (a). What is Cache memory- Explain working of a Cache memory. (10 marks)
      (b). What is pipelining? Explain instruction pipelining. (10 marks)
      (c). Describe interrupt driven I/O. (10 marks)

    2. Explain working of DMA data transfer. Compare it with programmed I/O and interrupt driven data transfer. (20 Marks)

    3. Explain the difference between hardwired control and micro programmed control. Is it possible to have a hardwired control associated with a control memory? (20 Marks)

    1. Explain the block diagram of an I/O interface unit. (20 marks)

    2. Using a diagram, explain the following steps executing of a program

      1. Fetch

      2. Decode

      3. Execute (20 marks)

    Grading Scheme

    Marks to be distributed as indicated against each question in the answers students will provide


    1.(a). Cache memory

    Is memory that stores program instructions that are frequently re-referenced by software during operation. Fast access to these instructions increases the overall speed of the software program.

    (b). Pipelining

    A form of computer organization in which successive steps of an instruction sequence are executed in turn by a sequence of modules able to operate concurrently, so that another instruction can be begun before the previous one is finished.

    Instruction pipelining is a technique that implements a form of parallelism called instruction- level parallelism within a single processor. It therefore allows faster CPU throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate.

    (c) . Interrupt driven I/O

    The CPU works on its given tasks continuously. When an input is available, such as when someone types a key on the keyboard, then the CPU is interrupted from its work to take care of the input data.

    2. Working of DMA data transfer

    • First the CPU programs the DMA controller by setting its registers so it knows what to transfer where

    • It also issues a command to the disk controller telling it to read data from the disk into its internal buffer and verify the checksum.

    • When valid data are in the disk controller’s buffer, DMA can begin. The DMA controller initiates the transfer by issuing a read request over the bus to the disk controller . This read request looks like any other read request, and the disk controller does not know (or care) whether it came from the CPU or from a DMA controller. Typically, the memory address to write to is on the bus’ address lines, so when the disk controller fetches the next word from its internal buffer, it knows where to write it. The write to memory is another standard bus cycle.

    • When the write is complete, the disk controller sends an acknowledgement signal to the DMA controller, also over the bus. The DMA controller then increments the memory address to use and decrements the byte count. If the byte count is still greater than 0, steps 2 through 4 are repeated until the count reaches 0.

    • At that time, the DMA controller interrupts the CPU to let it know that the transfer is now complete. When the operating system starts up, it does not have to copy the disk block to memory; it is already there.

    Comparing DMA with programmed I/O and interrupt driven data transfer

    Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control to access registers or memory on a device. while the device interrupts the CPU when new data has arrived and is ready to be retrieved by the system processor. The actual actions to perform depend on whether the device uses I/O ports, memory mapping.

    3. Micro programmed control is a control mechanism to generate control signals by using a memory called control storage (CS), which contains the control signals. Although micro programmed control seems to be advantageous to CISC machines, since CISC requires systematic development of sophisticated control signals, there is no intrinsic difference between these 2 control mechanisms.

    Hardwired control is a control mechanism to generate control signals by using appropriate finite state machine (FSM). The pair of “microinstruction-register” and “control storage address register” can be regarded as a “state register” for the hardwired control. Note that the control storage can be regarded as a kind of combinational logic circuit. We can assign any 0, 1 values to each output corresponding to each address, which can be regarded as the input for a combinational logic circuit.


    5. Is the process by which a computer or a virtual machine performs the instructions of a computer program. The instructions in the program trigger sequences of simple actions on the executing machine.

    Fetch; first step the CPU carries out is to fetch some data and instructions (program) from main memory then store them in its own internal temporary memory areas. These memory areas are called ‘registers’. The computer fetches the instruction from its memory and then executes it. This is done repeatedly from when the computer is booted up to when it is shut down. When the instruction has been decoded, the CPU can carry out the action that is needed. This is called executing the instruction. The CPU is designed to understand a set of instructions - the instruction set.

    Decode; The next step is for the CPU to make sense of the instruction it has just fetched. This process is called ‘decode’. The CPU is designed to understand a specific set of commands.

    These are called the ‘instruction set’ of the CPU. Each make of CPU has a different instruction set. The CPU decodes the instruction and prepares various areas within the chip in readiness of the next step.

    Execute; This is the part of the cycle when data processing actually takes place. The instruction is carried out upon the data (executed). The result of this processing is stored in yet another register. Once the execute stage is complete, the CPU sets itself up to begin another cycle once more.

    6.1: Final Exam is shared under a CC BY-SA license and was authored, remixed, and/or curated by Harrison Njoroge.

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